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NJU6635 preliminary 00/01/15 16-character 2-line dot matrix lcd controller driver general description the NJU6635 is a 1chip dot matrix lcd controller driver for up to 16-character 2-line display with double height function. it contains microprocessor interface circuits, instruction decoder controller, character generator rom/ram and common and segment drivers. the bleeder resistance generates for lcd bias voltage internally. the cr oscillator incorporates c and r, therefore no external components for oscillation are required. the microprocessor interface circuits which operate 2mhz frequency, can be connected directly to 4/8bit microprocessor. the character generator consists of 9,600 bits rom and 32 x 5 bits ram. the standard version rom is coded with 240 characters including capital and small letter fonts. the 16-common and 80-segment drive up to 16-character 2-line lcd panel which divided two common electrode blocks. the rectangle outlook is very applicable to cog. features 16-character 2-line dot matrix lcd controller driver 4/8 bit microprocessor direct interface display data ram :32 x 8 bits : maximum 16-character 2line display character generator rom :9,600 bits ; 240 characters for 5 x 8 dots character generator ram :32 x 5 bits ; 4 patterns( 5 x 8 dots) microprocessor direst accessing to display data ram and character generator ram high voltage lcd driver :16-common / 80-segment duty ratio :1/16 duty maximum display characters ; 32 characters useful instruction set clear display, returns home, display on/off cont, cursor on/off cont, display blink, cursor shift, character shift, double height function. power on reset / hardware reset function oscillation circuit on chip bleeder resistance on chip low power consumption operating voltage --- +5v package outline --- bumped chip c-mos technology package outline NJU6635ch
NJU6635 pad location chip size :5.49 x 1.37mm bump size :45 x 83 m chip center :x=0 m, y=0 m bump height :17.5 m typ. bump material :au 1
NJU6635 pad coordinates chip size(5490 m x 1370 m) pad name pad name pad no. a mode b mode x= um y= um pad no. a mode b mode x= um y= um 1 dmy_1 dmy_1 -2435 -534 70 seg 28 seg 53 750 541 2 osc1 osc1 -2282 -534 71 seg 29 seg 52 690 541 3 osc2 osc2 -2061 -534 72 seg 30 seg 51 630 541 4 v ss v ss -1916 -534 73 seg 31 seg 50 570 541 5 v ss v ss -1856 -534 74 seg 32 seg 49 510 541 6 v ss v ss -1796 -534 75 seg 33 seg 48 450 541 7 v dd v dd -1661 -534 76 seg 34 seg 47 390 541 8 v dd v dd -1601 -534 77 seg 35 seg 46 330 541 9 v dd v dd -1541 -534 78 seg 36 seg 45 270 541 10 v 5 v 5 -1407 -534 79 seg 37 seg 44 210 541 11 v 5 v 5 -1347 -534 80 seg 38 seg 43 150 541 12 v 5 v 5 -1287 -534 81 seg 39 seg 42 90 541 13 v 3 v 3 -1138 -534 82 seg 40 seg 41 30 541 14 v 2 v 2 -918 -534 83 seg 41 seg 40 -30 541 15 reset reset -689 -534 84 seg 42 seg 39 -90 541 16 rs rs -468 -534 85 seg 43 seg 38 -150 541 17 rw rw -239 -534 86 seg 44 seg 37 -210 541 18 e e 336 -534 87 seg 45 seg 36 -270 541 19 db 0 db 0 561 -534 88 seg 46 seg 35 -330 541 20 db 1 db 1 820 -534 89 seg 47 seg 34 -390 541 21 db 2 db 2 1049 -534 90 seg 48 seg 33 -450 541 22 db 3 db 3 1308 -534 91 seg 49 seg 32 -510 541 23 db 4 db 4 1537 -534 92 seg 50 seg 31 -570 541 24 db 5 db 5 1797 -534 93 seg 51 seg 30 -630 541 25 db 6 db 6 2025 -534 94 seg 52 seg 29 -690 541 26 db 7 db 7 2285 -534 95 seg 53 seg 28 -750 541 27 dmy_2 dmy_2 2435 -534 96 seg 54 seg 27 -810 541 28 dmy_3 dmy_3 2600 -390 97 seg 55 seg 26 -870 541 29 dmy_4 dmy_4 2600 -330 98 seg 56 seg 25 -930 541 30 dmy_5 dmy_5 2600 -270 99 seg 57 seg 24 -990 541 31 dmy_6 dmy_6 2600 -210 100 seg 58 seg 23 -1050 541 32 com 1 com 9 2600 -150 101 seg 59 seg 22 -1110 541 33 com 2 com 10 2600 -90 102 seg 60 seg 21 -1170 541 34 com 3 com 11 2600 -30 103 seg 61 seg 20 -1230 541 35 com 4 com 12 2600 30 104 seg 62 seg 19 -1290 541 36 com 5 com 13 2600 90 105 seg 63 seg 18 -1350 541 37 com 6 com 14 2600 150 106 seg 64 seg 17 -1410 541 38 com 7 com 15 2600 210 107 seg 65 seg 16 -1470 541 39 com 8 com 16 2600 270 108 seg 66 seg 15 -1530 541 40 dmy_7 dmy_7 2600 330 109 seg 67 seg 14 -1590 541 41 dmy_8 dmy_8 2600 390 110 seg 68 seg 13 -1650 541 42 dmy_9 dmy_9 2435 541 111 seg 69 seg 12 -1710 541 43 seg 1 seg 80 2370 541 112 seg 70 seg 11 -1770 541 44 seg 2 seg 79 2310 541 113 seg 71 seg 10 -1830 541 45 seg 3 seg 78 2250 541 114 seg 72 seg 9 -1890 541 46 seg 4 seg 77 2190 541 115 seg 73 seg 8 -1950 541 47 seg 5 seg 76 2130 541 116 seg 74 seg 7 -2010 541 48 seg 6 seg 75 2070 541 117 seg 75 seg 6 -2070 541 49 seg 7 seg 74 2010 541 118 seg 76 seg 5 -2130 541 50 seg 8 seg 73 1950 541 119 seg 77 seg 4 -2190 541 51 seg 9 seg 72 1890 541 120 seg 78 seg 3 -2250 541 52 seg 10 seg 71 1830 541 121 seg 79 seg 2 -2310 541 53 seg 11 seg 70 1770 541 122 seg 80 seg 1 -2370 541 54 seg 12 seg 69 1710 541 123 dmy_10 dmy_10 -2435 541 55 seg 13 seg 68 1650 541 124 dmy_11 dmy_11 -2600 390 56 seg 14 seg 67 1590 541 125 dmy_12 dmy_12 -2600 330 57 seg 15 seg 66 1530 541 126 com 16 com 8 -2600 270 58 seg 16 seg 65 1470 541 127 com 15 com 7 -2600 210 59 seg 17 seg 64 1410 541 128 com 14 com 6 -2600 150 60 seg 18 seg 63 1350 541 129 com 13 com 5 -2600 90 61 seg 19 seg 62 1290 541 130 com 12 com 4 -2600 30 62 seg 20 seg 61 1230 541 131 com 11 com 3 -2600 -30 63 seg 21 seg 60 1170 541 132 com 10 com 2 -2600 -90 64 seg 22 seg 59 1110 541 133 com 9 com 1 -2600 -150 65 seg 23 seg 58 1050 541 134 dmy_13 dmy_13 -2600 -210 66 seg 24 seg 57 990 541 135 dmy_14 dmy_14 -2600 -270 67 seg 25 seg 56 930 541 136 dmy_15 dmy_15 -2600 -330 68 seg 26 seg 55 870 541 137 dmy_16 dmy_16 -2600 -390 69 seg 27 seg 54 810 541
NJU6635 block diagram instruction decoder ( id ) display data ram (dd ram) 32 x 8 bits address counter character generator (cg ram) 32 x 5bits character generator (cg ram) 9,600bits 80-bit shift resister 16-bit shift register 80-bit latch segment driver common driver cursor blink controller timing generator parallel to serial converter busy flag power on reset data register ( dr ) i/o buffer instruction re g ister ( dr ) cr osc osc1 osc2 rs r/w e v ss db 0 ? db 3 db 4 ? db 7 v ss v 5 v 4 v 3 v 2 v 1 v 3 v 2 v dd r 1 r 1 r 1 r 1 r 1 seg 1 ? seg 80 com 1 ? com 16 for lcd driver reset 4 4 8 8 8 8 7 5 5 7 7 8 8 8 5 80 80 80 16 16 7 5
NJU6635 terminal description pad no. a mode b mode symbol i/o f u n c t i o n 4 ? 9 4 ? 9 v dd , v ss ? power source : v dd = +5v, gnd : v ss = 0v 10 ? 14 10 ? 14 v 2 , v 3 , v 5 ? lcd driving power source 2 2 osc 1 i oscillation frequency adjustment terminals. normally open. (oscillation c and r are incorporated, osc freq.=540khz) 3 3 osc 2 o oscillation frequency adjustment terminals. normally open. this terminal also operates as the clock frequency monitor. 16 16 rs i resister selection signal input "0":instruction resister (writing) busy flag (reading) "1":data register (writing / reading) 17 17 r/w i read/write selection signal input "0":write "1":read 18 18 e i read/write activation signal input 26 ? 23 26 ? 23 db 7 ? db 4 i/o 3-state data bus(upper) to transfer the data between mpu and NJU6635 . db 7 is also used for the busy flag reading. 19 ? 22 19 ? 22 db 3 ? db 0 i/o 3-state data bus(lower) to transfer the data between mpu and NJU6635 . in serial and 4bit parallel mode, these terminals are not used and should be open. 32 ? 39, 126 ? 133 133 ? 126, 39 ? 32 com 1 ? com 16 o lcd common driving signal terminals 43 ? 122 122 ? 43 seg 1 ? seg 80 o lcd segment driving signal terminals 15 15 reset i reset terminal. when the ?l? level input over than 1.2ms to this terminal, the system will be reset.(f osc =540khz) 1, 27 ? 31, 40 ? 42, 123 ? 125, 134 ? 137 1, 27 ? 31, 40 ? 42, 123 ? 125, 134 ? 137 dummy 1 ? dummy 15 o dummy terminal these terminals are electrically open.
NJU6635 functional description (1)description for each blocks (1-1)register the NJU6635 incorporates two 8-bit registers, an instruction register (ir) and a data register (dr). the register (ir) stores instruction codes such as ?clear display? and ?return home?, and address data for display data ram (dd ram) and character generator ram (cg ram). the mpu can write the instruction code and address data to the register (ir), but it can not read out from the register (ir). the register (dr) is a temporary storing register, the data in the register (dr) is written into the dd ram or cg ram and read out from the dd ram or cg ram. the data in the register (dr) written by the mpu is transferred from the register automatically to the dd ram or cg ram by internal operation. after reading the data in the register (dr) by the mpu, the next address data in the dd ram or cg ram is transferred automatically to the register (dr) for the next mpu reading. these two registers are selected by the selection signal rs as shown below: table 1. register operation control by rs and r/w signals. table 1. register operation rs r/w operation 0 0 write 0 1 read busy flag (db 7 ) and address counter (db 0 to db 7 ) 1 0 write (dr to dd or cg ram) 1 1 read (dd or cg ram to dr) (1-2)busy flag (bf) when the internal circuits are operating, the busy flag is ?1?, and any instruction reading is inhibited. the busy flag (bf) is output from db 7 when rs=?0? and r/w=?1? as shown in table 1. the next instruction should be written after busy flag (bf) goes to ?0?. (1-3)address counter(ac) the address counter (ac) addresses the dd ram and cg ram. when the address setting instruction is written into the register (ir), the address information is transferred from register (ir) to the counter (ac). the selection of either the dd ram or cg ram is also determined by this instruction. after writing (or reading) the display data to (or from) the dd ram or cg ram, the counter (ac) increments (or decrements) ?1? automatically. the address data in the counter (ac) is output from db 6 to db 0 when rs=?0? and r/w=?1? as shown in table 1. (1-4)display data ram (dd ram) the display data ram (dd ram) consisting of 32 x 8 bits stores up to 32-character display data represented in 8-bit code. the dd ram address data set in the address counter (ac) is represented in hexadecimal. higher order bit lower order bit (example) dd ram address ? 08 ? ac ac 6 ac 5 ac 4 ac 3 ac 2 ac 1 ac 0 0 0 0 1 0 0 0 0 hexadecimal 8 hexadecimal
NJU6635 (1-4-1)16-character 2-line display the NJU6635 has two kinds of addressing mode as ? addressing mode 1 ? and ? addressing mode 2 ? which is determined by the function set instruction (a=0 and 1). ?addressing mode 1? uses sequential address of (00) h through (1f) h for front half 16-character and last half 16-character. ?addressing mode 2 ? does not use sequential address like as (00) h through (1f) h and (40) h through (4f) h for front half 16-character and last half 16-character respectively. ? addressing mode 1: a=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 display position 1st line 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f dd ram address 2nd line 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f (hexadecimal) the relation between dd ram address and display position on the lcd shown below. [ left shift display ] (00) 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 (10) 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 00 [ right sift display ] 1f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e (0f) 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e (1f) ? addressing mode 2: a=1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 display position 1st line 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f dd ram address 2nd line 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f (hexadecimal) the relation between dd ram address and display position on the lcd shown below. [ left shift display ] (00) 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 00 (40) 41 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f [ right sift display ] 0f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e (0f) 4f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e (4f) (1-4-2)the relation between dd ram address and display position on the lcd shown below. (double height sized display function). correspondence between dd ram address and display position on the lcd panel. in case of double height size display function, the address of dd ram which is set as follows the display, operates as 16-character 1-line and the addressing mode is ignored. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 display position 1st line 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f dd ram address 2nd line 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f (hexadecimal) when the display shift is performed, the dd ram address changes as follows. [ left shift display ] (00) 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 00 (00) 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 00 [ right sift display ] 0f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e (0f) 0f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e (0f)
NJU6635 (1-5)character generator rom(cg rom) the character generator rom (cg rom) generates 5 x 8 dots character pattern represented in 8-bit character codes. the storage capacity is up to 240 kinds of 5 x 8 dots character pattern. the correspondence between character code and standard character pattern is shown in table 2. user-defined character pattern ( custom font ) are also available by mask option. table 2. cg rom character pattern ( rom version ?02 ) lower 4 bit (hexadecimal) u pp er 4 bit ( hexadecimal )
NJU6635 (1-6)character generator ram the character generator ram (cg ram) stores any kinds of character pattern in 5 x 8 dots written by the user program to display user?s original character pattern. the cg ram stores 4 kinds of character in 5 x 8 dots mode. to display user?s original character pattern stored in the cg ram, the address data (00) h ? (03) h should be written to the dd ram as shown in table 2. table 3. shows the correspondence among the character pattern, cg ram address and data. table 3. correspondence of cg ram address, dd ram character code and cg ram character pattern (5 x 8 dots) character code (dd ram data) cg ram address character pattern (cg ram data) 7 6 5 4 3 2 1 0 upper bit lower bit 4 3 2 1 0 upper bit lower bit 4 3 2 1 0 upper lower bit bit 0 0 0 0 ? ? 0 0 00 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 0 character pattern example (1) cursor position 0 0 0 0 ? ? 0 1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 0 0 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 character pattern example (2) cursor position 0 0 0 0 0 1 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 0 0 0 0 ? ? 1 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 notes: 1. character code bits 0 and 1 correspond to the cg ram address 3 and 4 ( 2bits : 4 patterns). 2. cg ram address 0, 1 and 2 designate a character pattern line position. the 8th line is the cursor position and the display is performed by logical or with cursor. therefore, in case of the cursor display, the data of 8th line should be ?0?. if there is ?1? in the 8th line, the bit ?1? is always displayed on the cursor position regardless of cursor existence. 3. character pattern row position corresponding to the cg ram data bits 0 to 4 are all shown above. the bits 5 to 7 of the cg ram do not exist. 4. cg ram character patterns are selected when character code bits 4 to 7 are all ?0? and addressed by character code bits 0 and 1. therefore the address (00) h , (04) h , (08) h and (0c) h , select the same character pattern as shown in table 2 and table 3. 5. ?1? for cg ram data corresponds to display on and ?0? to display off.
NJU6635 (1-7)timing generator the timing generator generates a timing signals for the dd ram, cg ram, cg rom and other internal circuit operation. ram read timing for the display and internal operation timing for mpu access are separately generated, so that they may not interfere with each other. therefore, when the data write to the dd ram for example, there will be undesirable influence, such as flickering, in areas other than the display area. (1-8)lcd driver lcd driver consists of 16-common driver and 80-segment driver. the 80 bits of character pattern data are shifted in the shift-register and latched when the 40 bits shift performed completely. this latched data controls display driver to output lcd driving waveform. (1-9)cursor blinking control circuit this circuits controls cursor on/off and cursor position character blinks. the cursor or blinks appears in the digit position at the dd ram address set in the address counter(ac). when the address counter is (08) h , a cursor position is shown as follows: ac 6 ac 5 ac 4 ac 3 ac 2 ac 1 ac 0 ac 0 0 0 1 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 display position 1st line 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f dd ram address 2nd line 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f (hexadecimal) note) the cursor or blinks appears when the address counter (ac) selects the cg ram. but the displayed cursor and blink are meaningless. if the ac stores the cg ram address data, the cursor and blink are displayed in the meaningless position. cursor position
NJU6635 (2)power on initialization by internal circuits (2-1) initialization by internal reset circuits the NJU6635 is initialized automatically by the internal power on initialization circuits when the power is turned on. in the internal power on initialization, following instructions are executed. during the internal power on initialization, the busy flag (bf) is ?1? and this status is kept 10ms after v dd = 4.5v. initialization flow is shown below: clear display function set display on/off control entry mode set note) if the condition of power supply rise time described in the electrical characteristics is not satisfied, the internal power on initialization circuits will not operate and initialization will not be performed. in this case, the initialization by mpu software is required. (2-2) initialization by hardware the NJU6635 incorporates reset terminal to initialize the all system. when the ?l? level input over than 1.2ms to the reset terminal, the reset sequence is executed. in this time, the busy signal output during 10ms after reset terminal goes to ?h?. ? reset operation ? operation timing dl=1 :8-bit long interface data a=0 :addressing mode 1 m0=0 :a mode m1=0 :32-character 1-line e=0 :normal display mode d=0 :display off c=0 :cursor off b=0 :cursor blink off i/d=1 :increment by 1 s=0 :no shift external reset signal busy over 1.2ms 10ms counter output rs-f/f output internal reset signal reset counter c rst q system clock c rst q power no reset system reset rs-f/f
NJU6635 (3) instructions the NJU6635 incorporates two resisters, which are instruction register (ir) and a data register (dr). these two registers store control information temporarily to allow interface between NJU6635 and mpu or peripheral ics operating different cycles. the operation of NJU6635 is determined by this control signal from mpu. the control information includes register selection signals (rs), read/write signals (r/w) and data bus signals (db 0 to db 7 ). table 5. shows each instruction and its operating time. note) the execution time mentioned in table 5. is based on fcp or f osc =540khz. if the oscillation frequency is changed, the execution time is also changed. table 5. table of instruction c o d e instruction rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 description exec time (f osc =540khz)* maker test 0 0 0 0 0 0 0 0 0 0 all ?0? code is using for maker testing. ? clear display 0 0 0 0 0 0 0 0 0 1 display clear and sets dd ram address 0 in ac. 315.9 s return home / font size set 0 0 0 0 0 0 0 0 1 e sets dd ram address 0 in ac and returns display being shifted to original position. dd ram contents remain unchanged. 18.5 s entry mode set 0 0 0 0 0 0 0 1 i/d s sets cursor move direction and species shift of display are performed in data read/write. i/d=1:increment, i/d=d:decrement,s=1:accopa nies display shift. 18.6 s display on/off control 0 0 0 0 0 0 1 d c b sets of display on/off(d), cursor on/off(c) and blink of cursor position character(b) 18.6 s cursor or display shift 0 0 0 0 0 1 s/c r/l ? ? move cursor and shifts display without changing dd ram contents. s/c=1 : display shift s/c=0 : cursor shift r/l=1 : shift to right r/l=0 : shift to the left 28 s function set 0 0 0 0 1 dl a ? m1 m0 sets interface data length(dl), display address mode(a) dl=1 : 8 bits, dl=0 : 4 bits a=0 : addressing mode 1 a=1 : addressing mode 2 m1=0 : 32-character 1-line m1=1 : 16-character 2-line m0=0 : pin configuration mode a m0=1 : pin configuration mode b 18.6 s set cg ram address 0 0 0 1 ? cg ram address sets cg ram address. after this instruction, the data is transferred on cg ram. 18.6 s set dd ram address 0 0 1 dd ram address sets dd ram address. after this instruction, the data is transferred on dd ram. 18.5 s ac read busy flag & address 0 1 bf ? ? ac read busy flag and ac contents. bf=1 : internally operating bf=0 : can accept instruction 0 s write data(dd ram) write data to cg or dd or mk ram 1 0 ? ? ? (cg ram) writes data into cg or dd ram. 18.6 s read data(dd ram) read data from cg or dd or mk ram 1 1 ? ? ? (cg ram) reads data from cg or dd ram 28 s explanation of abbreviation dd ram : display data ram, cg ram : character generator ram acg : cg ram address, add : dd ram address, corresponds to cursor address ac : address counter used for both dd and cg ram ? =don?t care
NJU6635 (3-1) description of instruction a) maker test rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 0 0 0 0 0 0 all ?0? code in 4-bit length is using device testing mode ( only for maker ). therefore, please avoid all ?0? input or no meaning enable signal input at data ?0? ( especially please pay attention to the output condition of enable signal when the power turns on ). all ?0? code in 8-bit length is usable for nop ( not operating instruction ). b) clear display rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 0 0 0 0 0 1 clear display instruction is executed when the code ?1? is written into db 0 . in case of normal display mode, when this instruction is executed, the space code (20) h is written into every dd ram address, the dd ram address 0 is set into the address counter and entry mode is set an increment. if the cursor or blink are displayed, they are returned to the left end of the lcd. the s of entry mode and cg ram data does not change. in case of double height mode, when this instruction is executed, the space code (20) h is written into dd ram address,(00) h to (0f) h . note: the character pattern for character code (20) h must be blank code in the user-defined character pattern( custom font ). c) return home / font size set rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 0 0 0 0 1 e return home instruction is executed when the code ?1? is written into db 1 . when this instruction is executed, the dd ram address 0 is set to address counter. display is returned to the original position if shifted, the cursor or blink is returned to the left end of the lcd. if the cursor or blink are on the display, the dd ram contents are not changed. the normal display mode is executed when the code ?0? is written into db 0 . the double height mode function is set by writing ?1? into db 0 . the character of dd ram address, (00) h to (0f) h , are expanded to double height size ( 5 x 16 dots ) and ?return home? function is operated. in this time, access from (10) h to (1f) h or (40) h to (4f) h of dd ram address is not available but the data in ram are kept. therefore, when the display mode returns from double height to normal, the kept data in ram displays again. in case of no display, ?clear display? should be operated before transition from normal mode to double height. the cursor size is also expanded to 5 x 2 dots. double height sized display function and normal are not operated in the mean time. the font in double height mode is some as normal. e function 0 normal display mode (font size : 5 x 8dots) 1 double height sized display mode (font size : 5 x 16 dots) in case of dd ram address : (00) h to (0f) h .
NJU6635 d) entry mode set rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 0 0 0 1 i/d s entry mode set instruction which sets cursor moving direction and display shift on/off, is executed when the code ?1? is written into db 2 and the codes of (i/d) and (s) are written into db 1 (i/d) and db 0 (s) as shown below. (i/d) sets the address increment or decrement, and the (s) sets the entire display shift in the dd ram writing. i/d function 0 address increment : the address of the dd ram increment ( +1) when the read/write, and the cursor or blink moves to the right. 1 address decrement : the address of the dd or cg ram decrement ( -1) when the read/write, and the cursor or blink move to the left. s function 1 entire display shift. the shift direction is determined by i/d: shift to the left at i/d=1 and shift to the right at the i/d=0. the shift is operated with only the character, so that it looks as if the cursor stands still and the display moves. the display does not shift when reading from the dd ram and writing/reading into/from cg ram. 0 the display does not shifting e) display on/off control rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 0 0 1 d c b display on/off control instruction which controls the display on/off, the cursor on/off and the cursor position character blink, is executed when the code ?1? is written into db 3 and the codes of (d), (c) and (b) are written into db 2 (d), db 1 (c) and db0(b) as shown below. d function 1 display on. 0 display off. in this mode, the display data remains in the dd ram so that it is retrieved immediately on the display when the d change to 1. c function 1 cursor on. the cursor is displayed by 5 dots on the 8th line. 0 cursor off. even if the display data write, the i/d etc does not change. b function 1 the cursor position character is blinking. blinking rate is 303.4ms at f osc =540khz. the blink is displayed alternatively with all on (it means all black) and characters display. the cursor and the blink can be displayed simultaneously. 0 the character does not blink.
NJU6635 ? normal display mode ? double height sized display mode f) cursor display shift rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 0 1 s/c r/l ? ? the cursor/display shift instruction shifts the cursor position or display the right or left without writing reading display data. the contents of address counter (ac) is not changed by operation of display shift only. this instruction is executed when the code ?1? is written into db 4 and the codes of (s/c) and (r/l) are written into db 3 (s/c) and db 2 (r/l) as shown below. s/c r/l function 0 0 shifts the cursor position to the left ((ac) is decrement by 1) 0 1 shifts the cursor position to the right ((ac) is incremented by 1) 1 0 shifts the entire display to the left and the cursor follows it. 1 1 shifts the entire display to the right and the cursor follows it. ! " " " ! " ! ! ! " " ! ! ! " " ! ! ! " " " " " " " ! ! ! " " ! ! ! " " " " " " character font 5 x 7dots (1) cursor display example ! " " " ! " ! ! ! " " ! ! ! " " ! ! ! " " " " " " " ! ! ! " " ! ! ! " ! ! ! ! ! alternating display (2) blink display example " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " ! " " " ! ! " " " ! " ! ! ! " " ! ! ! " " ! ! ! " " ! ! ! " " ! ! ! " " ! ! ! " " " " " " " ! ! ! " " ! ! ! " " ! ! ! " " ! ! ! " " " " " " " " " " " character font 5 x 14dots (3) cursor display example ! " " " ! ! " " " ! " ! ! ! " " ! ! ! " " ! ! ! " " ! ! ! " " ! ! ! " " ! ! ! " " " " " " " ! ! ! " " ! ! ! " " ! ! ! " " ! ! ! " ! ! ! ! ! ! ! ! ! ! " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " alternating display (2) blink display example ? =don?t care
NJU6635 g) function set rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 1 dl a ? m1 m0 function set instruction which sets the interface data length, the addressing mode for the dd ram, 1-line or 2-line display, and pin configuration mode, is executed when the code ?1? is written into db 5 and the codes of (dl), (a), (m1) and (m0) are written into db 4 (dl), db 3 (a), db 1 (m1), and db 0 (m0) as shown below (character font is fixed 5 x 8 dots). note) this function set instruction must be performed at the head of the program prior to all other instructions (except busy flag/address read). this function set instruction can not be executed afterwards unless the interface data length change. dl function 1 set the interface data length to 8 bits (db 7 to db 0 ) 0 set the interface data length to 4 bits (db 7 to db 4 ) a couple of data must be sent or received. a function 0 set the addressing mode 1 for the dd ram 1 set the addressing mode 2 for the dd ram m1 function 0 set the 32-character 1-line display 1 set the 16-character 2-line display m0 function 0 set the pin configuration mode a for common and segment driver (refer to cord.) 1 set the pin configuration mode b for common and segment driver (refer to cord.) h) set cg ram address rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 1 ? a a a a a higher order bit lower order bit set cg ram address instruction is executed when the code ?1? is written into db 6 and the address is written into db 4 to db 0 as shown above. the address data mentioned by binary code ?aaaaa ? is written into the address counter (ac) together with the cg ram addressing condition. after this instruction, the data writing/reading is performed into/from the cg ram. cg ram address cg ram : (00) h ? (1f) h ? =don?t care
NJU6635 i) set dd ram address rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 1 a a a a a a a higher order bit lower order bit set dd ram address instruction is executed when the code ?1? is written into db 7 and the address is written into db 6 to db 0 as shown above. the address data mentioned by binary code ?aaaaaaa ? is written into the address counter (ac) together with the dd ram addressing condition. after this instruction, the data writing/reading is performed into/from the dd ram. the dd ram address is indicated as follows, which is available for dd ram address only. normal mode condition dd ram address dd ram 1-line : (00) h ? (0f) h dd ram 2-line (addressing mode 1) : (10) h ? (1f) h dd ram 2-line (addressing mode 2) : (40) h ? (4f) h double height size display condition dd ram address dd ram 1-line : (00) h ? (0f) h j) read busy flag & address rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 1 bf a a a a a a a higher order bit lower order bit this instruction reads out the internal status of the NJU6635 . when this instruction is executed, the busy flag (bf) which indicates the internal operation, is read out from db 7 and the address of cg ram or dd ram is read out from db 6 to db 0 (an address for cg ram or dd ram is determined by the previous instruction). (bf)=1 indicates that internal operation is in progress. the next instruction is inhibited w hen (bf)=1. check the (bf) status before the next write operation. k) write data to cg or dd ram ? write data to cg ram rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 ? ? ? d d d d d higher order bit lower order bit ? write data to dd ram rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 d d d d d d d d higher order bit lower order bit write data to cg ram or dd ram instruction is executed when the code ?1? is written into (rs) and code ?0? is written into (r/w). by the execution of this instruction, the binary 5-bit data ?ddddd? are written into the cg ram, and the binary 8-bit data ?dddddddd? are written into the dd ram. the selection of the cg ram or dd ram is determined by the previous instruction. after this instruction execution, the address increment(+1) or decrement(-1) is performed automatically according to the entry mode set. and the display shift is also executed according to the previous entry mode set. ? =don?t care
NJU6635 l) read data from cg or dd ram ? read data to dd ram rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 1 d d d d d d d d higher order bit lower order bit ? read data to cg ram rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 ? ? ? d d d d d higher order bit lower order bit read data to cg ram or dd ram instruction is executed when the code ?1? is written into (rs) and (r/w). by the execution of this instruction, the binary 5-bit data ?ddddd? are read out from cg ram, and the binary 8-bit data ?dddddddd? are read out from dd ram. the selection of the cg ram or dd ram is determined by the previous instruction. before executing this instruction, either the cg ram address set or dd ram address set must be executed, otherwise the first read out data invalidated. when this instruction is serially executed, the next address data is normally read from the second read. the address set instruction is not required if the cursor shift instruction is executed just beforehand (only dd ram reading). the cursor shift instruction has same function as the dd ram address set, so that after reading the dd ram, the address increment or decrement is executed automatically according to the entry mode. but display shift does not occur regardless of the entry mode. note) the address counter (ac) is automatically incremented by 1 after write instructions to either of the cg ram or dd ram. even if the read instruction is executed after this instruction, the addressed data can not be read out correctly. for a correct data read out, either the address set instruction or cursor shift instruction (only with dd ram) must be implemented just before this instruction or from the second time read out instruction execution if the read out instruction is executed 2 times consecutively. ? =don?t care
NJU6635 (3-2)initialization using the internal reset circuits a) 32-character 1-line in 8-bit operation addressing mode 1 (using internal reset circuits). at the 32-character 1-line display, the function set, on/off control and entry set instruction must be executed before the data input, as shown below. since the display shift operation changes only display position and the dd ram contents are unchanged, display data which are entered first can be output when the return home operation is performed. power on rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 function set 0 0 0 0 1 1 0 ? 0 0 rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 display on/off 0 0 0 0 0 0 1 1 1 0 control rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 entry mode set 0 0 0 0 0 0 0 1 1 0 write data to the cg or dd ram and set the instruction. b) 32-character 1-line in 4-bit operation addressing mode 1 (using internal reset circuits). in the 4-bit operation, the function set must be performed by the user programming. when the power is turned on, 8-bit operation is selected automatically, therefore the first input is performed under 8-bit operation. in this operation, full instruction can not input because of terminals db 0 to db 3 are no connection. therefore, same instruction must be rewritten on the rs, r/w and db 7 to db 4 , as shown below. since one operation is completed by the two accesses in the 4-bit operation mode, rewrite is required to set the instruction code in full. 32-character 1-line in 4bit operation is shown as follows: power on rs r/w db 7 db 6 db 5 db 4 function set 0 0 0 0 1 0 rs r/w db 7 db 6 db 5 db 4 function set 0 0 0 0 1 0 0 0 0 ? 0 0 rs r/w db 7 db 6 db 5 db 4 display on/off 0 0 0 0 0 0 control 0 0 1 1 1 0 rs r/w db 7 db 6 db 5 db 4 entry mode set 0 0 0 0 0 0 0 0 0 1 1 0 write data to the cg or dd ram and set the instruction. initialized. no display appears. set the 8-bit operation, 32-character 1-line display, pin configuration mode a, addressing mode 1. turns on display and cursor. entire display is in space mode by the initialization. example for set address increment and cursor right shift when the data write to the dd or cg ram. initialized. no display appears. set the 4-bit operation. this step is executed in 8-bit mode set by initialization. turns on display and cursor. entire display is in space mode by the initialization. example for set address increment and cursor right shift when the data write to the dd or cg ram. set the 4-bit operation /32-character 1-line display, pin configuration mode a, addressing mode 1. the 4-bit o p eration starts from this ste p .
NJU6635 (3-3)initialization by instruction if the power supply conditions for the correct operation of the internal reset circuits are not method, the NJU6635 must be initialized by the instruction. a) initialization by instruction in 8-bit interface power on wait more than 15 ms after v dd rises to 4.5v rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 function set 0 0 0 0 1 1 ? ? ? ? wait more than 4.1ms rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 function set 0 0 0 0 1 1 ? ? ? ? wait more than 100 s rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 function set 0 0 0 0 1 1 ? ? ? ? rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 function set 0 0 0 0 1 1 0 ? 0 0 rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 display off 0 0 0 0 0 0 1 0 0 0 rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 display clear 0 0 0 0 0 0 0 0 0 1 rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 entry mode set 0 0 0 0 0 0 0 1 1 0 write data to the cg or dd ram and set the instruction. initialized. no display appears. function set (8-bit interface length) function set (8-bit interface length) function set (8-bit interface length) busy flag(bf) can not be checked before this step, but it can be checked after this step. a fter this step, busy flag(bf) check or longer waiting time than each instruction execution time is required. set the 8-bit operation, /addressing mode 1. example for set address increment and cursor right shift when the data write to the dd ram.
NJU6635 b) initialization by instruction in 4-bit interface power on wait more than 15ms after v dd rises to 4.5v rs r/w db 7 db 6 db 5 db 4 function set 0 0 0 0 1 1 wait more than 4.1ms rs r/w db 7 db 6 db 5 db 4 function set 0 0 0 0 1 1 wait more than 100 s rs r/w db 7 db 6 db 5 db 4 function set 0 0 0 0 1 1 rs r/w db 7 db 6 db 5 db 4 function set 0 0 0 0 1 0 rs r/w db 7 db 6 db 5 db 4 function set 0 0 0 0 1 0 0 0 0 ? 1 0 rs r/w db 7 db 6 db 5 db 4 display off 0 0 0 0 0 0 0 0 1 0 0 0 rs r/w db 7 db 6 db 5 db 4 display clear 0 0 0 0 0 0 0 0 0 0 0 1 rs r/w db 7 db 6 db 5 db 4 entry mode set 0 0 0 0 0 0 0 0 0 1 1 0 write data to the cg or dd ram and set the instruction. initialized. no display appears. function set (8-bit interface length) function set (8-bit interface length) function set (8-bit inter face length) busy flag(bf) can be not be checked before this step, but it can be checked after this step. a fter this step, busy flag (bf) check o r longer waiting time than each instruction execution time is required. set the 4bit operation / addressing mode 1 example for set address increment and cursor right shift when the data write to the dd or cg ram.
NJU6635 (4) lcd display NJU6635 incorporates bleeder resistance to generate the lcd display driving waveform. the bleeder resistance is set 1/5 bias suitable for 1/18 duty ratio and 1.5k ? per resistance. the decoupling capacitor should be connected between v dd and v 5 terminal. the value of capacitor is determined depending on the actual lcd panel display evaluation. lcd driving voltage vs. duty ratio duty ratio 1/16 bias 1/5 v 2 v dd -2/5v lcd v 3 v dd -3/5v lcd power supply v 5 v dd -v lcd ? the v lcd is maximum swing of lcd waveform. lcd driving voltage example note) power on or power off is in the following order. power on : v 5 should be turned on after the v dd turned on or at the same time. power off : v 5 should be turned off before the v dd turned off or at the same time. 1.5k ? v 5 v dd v lcd v 5 v 4 v 3 v 2 v 1 1.5k ? 1.5k ? 1.5k ? 1.5k ? NJU6635
NJU6635 (4-1) relation between oscillation frequency and lcd frame frequency. lcd frame frequency example mentioned below is based on 540khz oscillation. the clock for the lcd driving is using 270/2 khz (1 clock = 1.852 s) ? 1/16 duty 1 frame = 7.4 ( s) x 80 x 16 x 4 = 9.472(ms) frame frequency = 1/9.472(ms) = 105.6(hz) (5)interface with mpu NJU6635 can be interfaced with both of 4/8 bit mpu and the two-time 4-bit or one-time 8-bit data transfer is available. (5-1)8-bit mpu interface 1 2 3 80 clock 2 3 4 16 1 2 3 4 16 1 v lcd v 1 v 2 v 4 v ss 1 frame 1 frame no r/w rs e internal status db 7 o p eration busy busy busy flag check busy data data busy flag check busy flag check instruction writing instruction writing
NJU6635 (5-2)4-bit mpu interface when the interface length is 4-bit, the data transfer is performed by 4 lines connected to db 4 to db 7 (db 0 to db 3 are not used). the data transfer with the mpu is completed by the two-time 4-bit data transfer. the data transfer is executed in the sequence of upper 4-bit (the data db 4 to db 7 at 8-bit length) and lower 4-bit (the data db 0 to db 3 at 8-bit length). the busy flag check must be executed after two-time 4-bit data transfer (1 instruction execution). in this case the data of busy flag and address counter are also output twice. writing instruction into instruction register (ir) readout busy flag(bf) and address counter(ac) r/w rs e ir 7 db 7 db 6 db 5 db 4 ir 3 bf bf ac 3 dr 7 dr 3 ir 6 ir 2 ac 2 dr 6 dr 2 bf ir 5 ir 1 ac 1 dr 5 dr 1 bf ir 4 ir 0 ac 0 dr 4 dr 0 reading data register (dr) r/w rs e internal s tatus db 7 o p eration ir ir busy busy no a c d 7 d 3 instruction writing busy flag check a c busy flag check instruction writing
NJU6635 absolute maximum ratings (ta=25 c) p a r a m e t e r symbol r a t i n g s unit supply voltage v dd -0.3 to +7.0 v input voltage v in -0.3 to v dd +0.3 v operating temperature t opr -30 to +80 c storage temperature t stg -55 to +125 c note 1.) if the lsi is used on condition above the absolute maximum ratings, the lsi may be destroyed. using the lsi within electrical characteristics is strongly recommended for normal operation. use beyond the electric characteristics conditions will cause malfunction and poor reliability. note 2.) decoupling capacitor should be connected between v dd and v ss due to the stabilized operation for the lsi. note 3.) all voltage values are specified as v ss =0v note 4.) the relation v dd >v 5 v ss , v ss =0v must be maintained. electrical characteristics (v dd =4.5 to 5.5v, v ss =0v, ta=-20 to 75 c) parameter symbol symbol min typ max unit note operating volt. v dd v dd 4.5 5.0 5.5 v v ih1 2.3 ? v dd v input voltage 1 v il1 all input / output terminals except osc and e terminals ? ? 0.8 v 5 v ih2 v dd -1.0 ? v dd v input voltage 2 v il2 only osc terminals ? ? 1.0 v 5 v ih3 0.8 v dd ? v dd v input voltage 3 v il3 only e terminal ? ? 0.2 v dd v 5 i oh -i oh =0.205ma 2.4 ? ? v output voltage i ol i ol =1.6ma ? ? 0.4 v 6 driver on-resist. (com) r com i d =50 a (all com. term.) ? ? 20 k ? driver on-resist.(seg) r seg i d =50 a (all seg. term.) ? ? 30 k ? 9 input leakage current i li v in =0 to v dd -1 ? 1 a 7 pull-up resist current -i p v dd =5v 50 125 250 a operating current i dd v dd =5v f osc =540khz(cr oscillation) ? 2.0 3.6 ma 8 v 2 2.7 3.0 3.3 v lcd driving voltage v 3 v dd =5v, ta=25 c, v 5 =0v 1.7 2.0 2.3 v bleeder resistance r b v dd -v 5 =5v, ta=25 c 3.7 7.5 11.3 k ? oscillation frequency f osc v dd =5v, ta=25 c 270 540 810 khz lcd driving voltage v lcd v lcd = v dd -v 5 , v 5 v ss 3 ? v dd v 10
NJU6635 note 5) input / output structure except lcd driver are shown below: ? input terminal structure e terminal rs, r/w, reset terminals ? input / output terminal structure db 0 to db 7 terminals note 6.) apply to the input / output terminals. note 7.) except pull-up resistance current and output driver current. note 8.) except input / output current but including the current flow on bleeder resistance. note 9.) rcom and rseg are the resistance values between power supply terminals(v dd , v 2 , v 3 , v 5 ) and each common terminal (com 1 to com 16 ), and supply voltage (v dd , v 2 , v 3 , v 5 ) and each segment terminal(seg 1 to seg 80 ) respectively, and measured when the current id is flown on every common and segment terminals at the same time. note10.) apply to the output voltage from each com and seg are less than 0.15v against the lcd driving constant voltage (v dd ,v 5 ) at no load condition. ? bleeder resistance 1.5k ? v dd v 5 v 4 v 3 v 2 v 1 1.5k ? 1.5k ? 1.5k ? 1.5k ? NJU6635 v 5 v 2 v 3 v dd nmo pmos v ss ( pull-u p mos ) v ss v dd v dd nmos pmos v ss v dd v dd v dd v ss v ss nmos pmos pmos nmo pmos data enable
NJU6635 bus timing characteristics (v dd =4.5 to 5.5v, v ss =0v, ta=-20 to 75 c) ? write operation sequence (write from mpu to NJU6635 ) parameter symbol min max unit condition enable cycle time t cyce 500 ? ?high? level pw eh 220 ? enable pulse width low? level pw el 280 ? enable rise time, fall time t er , t ef ? 20 set up time rs, r/w-e t as 40 ? address hold time t ah 10 ? data set up time t dsw 60 ? data hold time t h 10 ? ns fig.1 fig.1 the timing characteristics of the bus write operating sequence.(write from mpu to NJU6635 ) ? read operation sequence ( read from NJU6635 to mpu) parameter symbol min max unit condition enable cycle time t cyce 500 ? ?high? level pw eh 220 ? enable pulse time low? level pw el 280 ? enable rise time, fall time t er , t ef ? 20 set up time rs, r/w-e t as 40 ? address hold time t ah 10 ? data delay time t ddr ? 240 data hold time t dhr 20 ? ns fig.2 fig.2 the timing characteristics of the bus write operating sequence.(write from NJU6635 to mpu) t cyce v il v il data v ih db 0 ? db 7 e r/w rs t dsw v ih t h v il v ih v il t er pw eh t ef v ih v il v ih v il v ih v il v il t as t ah t ah v il t cyce v ol v ol data v oh db 0 ? db 7 e r/w rs t ddr v oh t dhr v il v ih v il t er pw eh t ef v ih v ih v ih v il v ih v il v ih t as t ah t ah v il pw el pw el
NJU6635 ? the input condition when using the hardware reset circuit p a r a m e t e r symbol condition min typ max unit reset input ?low? level width t rsl f osc =540khz 1.2 ? ? ms input timing ? power supply condition when using the internal initialization circuit (ta=-20 to 75 c) p a r a m e t e r symbol condition min typ max unit power supply rise time t rdd ? 0.1 ? 5 ms power supply off time t off ? 1 ? ? ms 0.1ms t rdd 10ms t off 1ms note.) since the internal initialization circuits will not operate normally unless the above conditions are met, in such a case initialize by instruction(refer to initialization by the instruction). *t off specifies the power off time in a short period off o r cyclical on/off reset v rsl v il 0.2v 0.2v 4.5v 3v v d t rdd t off
NJU6635 lcd driving wave from NJU6635 1/16 duty driving 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v dd v 1 v 2 v 3 v 4 v 5 com 1 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 16 v dd v 1 v 2 v 3 v 4 v 5 com 2 v dd v 1 v 2 v 3 v 4 v 5 com 16 v dd v 1 v 2 v 3 v 4 v 5 seg 1 v dd v 1 v 2 v 3 v 4 v 5 seg 2
NJU6635 application circuits m0=0, m1=0 (32-character 1-line mode a) m0=0, m1=1 (16-character 2-line mode a)
NJU6635 m0=1, m1=0 (32-character 1-line mode b) m0=1, m1=1 (16-character 2-line mode b)
NJU6635 m0=0, m1=1 (16-character 1-line mode a) m0=1, m1=1 (16-character 1-line mode b)
n j u 66 35 m e m o [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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